This invention relates to architectures and fabrication processes for an integrated circuit die which directly increase the maximum number of bipolar logic cells that can be placed on the die.
In the prior art, it is conventional for an integrated circuit die manufacturer to provide a digital logic cell library which contains many different types of bipolar logic cells; and, those logic cells are selected and placed on the die as needed by a user. Some typical logic cells are an N-input AND gate (where N is 2, 3, or 4), an N-input OR gate, an N-input NAND gate, an N-input NOR gate, an N-input multiplexor, a flip-flop, input-output buffers, etc.
From a user's point of view, it is very desirable to be able to put more and more bipolar logic cells on a single die, since that enables the user to build a digital logic system with fewer die. But, several well known factors limit the maximum number of cells which the die can hold. These factors are: the smallest dimensions by which the bipolar transistors in each logic cell can be patterned, the largest size to which the die can be made while still maintaining an acceptable yield, the total number of die pads that can be provided on the die for signals and power, and the degree to which heat can be removed from the die during its operation.
In the most advanced bipolar die that are commercially available die today, the smallest feature dimension is about 0.75 um, the maximum die size is about 1.0cm, the total number of die pads is about 250, and total die power is about 15 watts. On such a die, each logic cell dissipates about 2.0-20.0 milliwatts, and the total number of logic cells is about 1600. This, for example, is achieved by the Motorola MCA 10,000 ECL die which is described in the "MCA3 ECL Series Design Manual", copyrighted by Motorola, 1990.
By comparison, the present invention is for use in very high power future die where the total number of bipolar logic cells is at least 10,000 and the resulting total die power is at least 75 watts. To be able to place such a large number of cells on one die, the smallest feature dimension must be reduced to about 0.40 um-0.60 um, and the die size must be increased to about 1.5 cm on a side. Also, to be able to place so many cells on a die, the present invention addresses still another factor, which is herein called a die power distribution factor. This factor doesn't even come into effect at low power levels of about 15 watts and less; but as power levels increase, it will cause a die to fail by reducing noise margin in the logic cells.